1. Technical Field
The present invention relates to integrated circuits and more particularly to a memory circuit with a programmable precharge circuit that reduces or eliminates half-select errors.
2. Description of the Related Art
Microprocessor yields can be determined by array yield parameters such as minimum voltage (Vmin), cell stability, and array performance. Different techniques have been proposed to improve the stability of static random access memory (SRAM) cells such as dynamic or dual cell power supplies based on read or write operations, usage of multi-threshold voltage (Vt) devices, or adding transistors to a six transistor (6T) SRAM cell.
An extension of this is the usage of an eight transistor (8T) cell where read and write ports are decoupled. However, the write port of an 8T SRAM suffers the same half select problems as that of 6T cells.
Referring to FIG. 1, prior art 6T SRAM cells 14 and 16 are illustratively shown. Cell 16 may suffer from a half select failure. Half select occurs when a wordline 12 is on while a column select is off. This leads to poor stability even when using fewer cells on bitlines 18 and 20. Due to the combination of active signals, the data in the cell may be partially or fully written to or discharged since the cell is half-selected (WL activates access transistors 30 even when the column is not selected).
Referring to FIG. 2, a 6T cell 40 is shown with a row selected while the column is not selected. A wordline (WL=1) is high and bitlines blc (bitline complement) and bit (bitline true) are clamped to the supply voltage VDD. In this case, charge may leak with respect to a memory cell portion 24, which employs a supply voltage VCS for transistors 26 and 28 of the cell 24. Access transistors 30 are employed to provide access to/from the bitlines (blc, blt) by the memory cell 24. When the cell 24 is not selected, VDD and Vcs, which have different values, cause a differential across access transistors 30. This results in current leakage to/from the memory cell 24 (half-select instability). Half-select occurs due to another internal ‘0’ storage node sharing charge with the bitline at VDD, through an access transistor 30.
In the case of an 8T cell, read and write operations may be carried out using separate wordlines. However, the write port is similar to the 6T cell described and suffers from the half-select problem.